This article is part of the series Design and Architectures for Signal and Image Processing 2009.

Open Access Research Article

Very Low-Memory Wavelet Compression Architecture Using Strip-Based Processing for Implementation in Wireless Sensor Networks

LiWern Chew*, WaiChong Chia, Li-minn Ang and KahPhooi Seng

Author Affiliations

Department of Electrical and Electronic Engineering, The University of Nottingham, 43500 Selangor, Malaysia

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EURASIP Journal on Embedded Systems 2009, 2009:479281  doi:10.1155/2009/479281

The electronic version of this article is the complete one and can be found online at:

Received:4 March 2009
Accepted:9 September 2009
Published:13 December 2009

© 2009 The Author(s).

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a very low-memory wavelet compression architecture for implementation in severely constrained hardware environments such as wireless sensor networks (WSNs). The approach employs a strip-based processing technique where an image is partitioned into strips and each strip is encoded separately. To further reduce the memory requirements, the wavelet compression uses a modified set-partitioning in hierarchical trees (SPIHT) algorithm based on a degree-0 zerotree coding scheme to give high compression performance without the need for adaptive arithmetic coding which would require additional storage for multiple coding tables. A new one-dimension (1D) addressing method is proposed to store the wavelet coefficients into the strip buffer for ease of coding. A softcore microprocessor-based hardware implementation on a field programmable gate array (FPGA) is presented for verifying the strip-based wavelet compression architecture and software simulations are presented to verify the performance of the degree-0 zerotree coding scheme.

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