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Open Access Research Article

Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding

Ke Xu* and Chiu-Sing Choy

Author Affiliations

Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong

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EURASIP Journal on Embedded Systems 2009, 2009:425173  doi:10.1155/2009/425173

The electronic version of this article is the complete one and can be found online at: http://jes.eurasipjournals.com/content/2009/1/425173


Received:11 July 2009
Revisions received:21 October 2009
Accepted:2 December 2009
Published:21 March 2010

© 2009 The Author(s).

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We present the design and VLSI implementation of a novel low-power bitstream-residual decoder for H.264/AVC baseline profile. It comprises a syntax parser, a parameter decoder, and an Inverse Quantization Inverse Transform (IQIT) decoder. The syntax parser detects and decodes each incoming codeword in the bitstream under the control of a hierarchical Finite State Machine (FSM); the IQIT decoder performs inverse transform and quantization with pipelining and parallelism. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, TAG method, zero-block skipping, and clock gating , are adopted and integrated throughout the bitstream-residual decoder. With innovative architecture, the proposed design is able to decode QCIF video sequences of 30 fps at a clock rate as low as 1.5 MHz. A prototype H.264/AVC baseline decoding chip utilizing the proposed decoder is fabricated in UMC 0.18 m 1P6M CMOS technology. The proposed design is measured under 1 V 1.8 V supply with 0.1 V step. It dissipates 76 W at 1 V and 253 W at 1.8 V.

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