This article is part of the series C-Based Design of Heterogeneous Embedded Systems.

Open Access Research Article

System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

Rainer Dömer*, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi and DanielD Gajski

Author Affiliations

Center for Embedded Computer Systems, University of California, Irvine, CA 92697-2625, USA

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EURASIP Journal on Embedded Systems 2008, 2008:647953  doi:10.1155/2008/647953


The electronic version of this article is the complete one and can be found online at: http://jes.eurasipjournals.com/content/2008/1/647953


Received:1 October 2007
Revisions received:4 March 2008
Accepted:10 June 2008
Published:26 June 2008

© 2008 The Author(s).

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE) which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.

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