This article is part of the series Embedded Digital Signal Processing Systems.

Open Access Research Article

A Shared Memory Module for Asynchronous Arrays of Processors

Michael J Meeuwsen*, Zhiyi Yu and Bevan M Baas

Author Affiliations

Department of Electrical and Computer Engineering, University of California, Davis, CA 95616-5294, USA

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EURASIP Journal on Embedded Systems 2007, 2007:086273  doi:10.1155/2007/86273

The electronic version of this article is the complete one and can be found online at:

Received:1 August 2006
Revisions received:20 December 2006
Accepted:1 March 2007
Published:9 May 2007

© 2007 Meeuwsen et al.

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.


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