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This article is part of the series Embedded Vision System.

Open Access Research Article

Dataflow-Based Mapping of Computer Vision Algorithms onto FPGAs

Mainak Sen1*, Ivan Corretjer1, Fiorella Haim1, Sankalita Saha1, Jason Schlessman2, Tiehan Lv2, Shuvra S Bhattacharyya1 and Wayne Wolf2

Author Affiliations

1 Department of Electrical and Computer Engineering, University of Maryland, College Park, MD 20742, USA

2 Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA

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EURASIP Journal on Embedded Systems 2007, 2007:049236  doi:10.1155/2007/49236

The electronic version of this article is the complete one and can be found online at: http://jes.eurasipjournals.com/content/2007/1/049236


Received:1 May 2006
Revisions received:8 October 2006
Accepted:9 October 2006
Published:28 January 2007

© 2007 Sen et al.

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We develop a design methodology for mapping computer vision algorithms onto an FPGA through the use of coarse-grain reconfigurable dataflow graphs as a representation to guide the designer. We first describe a new dataflow modeling technique called homogeneous parameterized dataflow (HPDF), which effectively captures the structure of an important class of computer vision applications. This form of dynamic dataflow takes advantage of the property that in a large number of image processing applications, data production and consumption rates can vary, but are equal across dataflow graph edges for any particular application iteration. After motivating and defining the HPDF model of computation, we develop an HPDF-based design methodology that offers useful properties in terms of verifying correctness and exposing performance-enhancing transformations; we discuss and address various challenges in efficiently mapping an HPDF-based application representation into target-specific HDL code; and we present experimental results pertaining to the mapping of a gesture recognition application onto the Xilinx Virtex II FPGA.

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